ASIC Engineer, Design
Meta

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge machine learning ASICs, capable of world class Inference and Training performance. We are looking for talented individuals with deep experience that span one or more of the key areas required to build successful world-class complex SoC and IP for data center applications.

ASIC Engineer, Design Responsibilities:

• Architecture exploration
• Micro-architecture development
• RTL development using Verilog, System Verilog and HLS
• Lint, CDC, Synthesis, & Power Optimization
• Soft and hard IP identification, selection and integration
• Collaboration with verification and emulation teams in test plan development and debug
• Collaboration with implementation team to close the design on timing and power

Minimum Qualifications:

• 5+ years of silicon development experience
• Track record of first-pass success in ASIC Development
• Experience with Verilog or System Verilog
• Experience in one of these skills: Micro-architecture and RTL development for complex control and data path IPs, OR Experience in SoC Micro-architecture, Design and Integration, OR Implementation, Power methodology development
• Experience working across multiple projects
• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

Preferred Qualifications:

• Experience in data path development
• Experience in CPU, NOC, Memory and Peripheral Subsystems
• Experience in HLS
• Experience with Synthesis, Timing Closure and Formal Verification Methodology
• Experience with Power Analysis and Optimization
• Experience with scripting languages (TCL, Python, Perl, Shell-scripting)

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